Methods of forming semiconductor devices having recesses

ABSTRACT

Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.13/424,234, filed Mar. 19, 2012, now U.S. Pat. No. 8,497,530, issuedJul. 30, 2013, which is a continuation of U.S. patent application Ser.No. 12/944,529, filed Nov. 11, 2010, now U.S. Pat. No. 8,138,526, issuedMar. 20, 2012, which is a divisional of U.S. patent application Ser. No.11/778,938, filed Jul. 17, 2007, now U.S. Pat. No. 7,879,659, issuedFeb. 1, 2011. The disclosure of each of the aforementioned applicationsand patents is hereby incorporated in its entirety by this reference.

TECHNICAL FIELD

Embodiments of the present invention relate generally to methods forfabricating so-called “fin” field-effect transistors, or “fin-FETs,”which protrude from an active surface of a fabrication substrate, andmore specifically, to methods for fabricating fin-FETs in which eachprotruding structure, or active-device region, includes two fins, aswell as to semiconductor device structures with dual fins.

BACKGROUND

The performance of silicon-based complementary metal-oxide-semiconductor(CMOS) transistors steadily improves as device dimensions shrink. Thedecreasing size of metal-oxide-semiconductor field-effect transistors(MOSFETs) provides improved integrated-circuit performance speed andcost per function. As channel lengths of MOSFET devices are reduced toincrease both the operation speed and the number of components per chip,the source and drain regions extend towards each other, occupying theentire channel area between the source and the drain. Interactionsbetween the source and drain of the MOSFET degrade the ability of thegate of the MOSFET to control whether the MOSFET is “on” or “off.” Inparticular, the threshold voltage and drive current decrease appreciablywith the channel length. This phenomenon is called the “short channeleffect.” The term “short channel effect,” as used herein, refers to thelimitations on electron drift characteristics and modification of thethreshold voltage caused by shortening trench lengths.

Double- or tri-gate transistors, such as vertical double-gatesilicon-on-insulator (SOI) transistors or fin-FETs, offer significantadvantages related to high drive current and high immunity to shorttrench effects. Conventionally, fin-FET devices have included single,unitary semiconductor structures that protrude from an active surface ofa substrate. Such a semiconductor structure is generally referred to asa “fin.” A polysilicon layer may be deposited over a central portion ofthe fin and patterned to form a pair of gates on opposite sides of thefin. Among the many advantages offered by fin-FETs is better gatecontrol at short gate lengths. Fin-FETs facilitate down-scaling of CMOSdimensions while maintaining acceptable performance.

With ever-decreasing semiconductor device feature sizes, the effects ofshortened channel lengths become increasingly problematic in thefabrication of semiconductor devices.

Methods of fabricating semiconductor devices to reduce short channeleffects and increase drive current, as well as improved fin-FETstructures, are desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2A are cross-sectional views of an embodiment of anintermediate semiconductor device structure of the present disclosureduring various stages of fabrication;

FIG. 2B is a plan view of the embodiment of the intermediatesemiconductor device structure shown in FIG. 2A;

FIGS. 3-8A are cross-sectional views of an embodiment of an intermediatesemiconductor device structure of the present disclosure during variousstages of fabrication;

FIG. 8B is a plan view of the embodiment of the intermediatesemiconductor device structure shown in FIG. 8A;

FIG. 9 is a perspective representation of the embodiment of theintermediate semiconductor device structure shown in FIG. 8A;

FIG. 10 is a perspective representation of a fin-FET device according toan embodiment of the present disclosure;

FIGS. 11-15 are cross-sectional views of various other embodiments ofdual fin structures; and

FIG. 16 is a schematic block diagram illustrating one embodiment of anelectronic system of the present disclosure that includes asemiconductor device as described hereinbelow.

DETAILED DESCRIPTION

An embodiment of a method of the present disclosure for fabricatingsemiconductor device structures with dual fins is disclosed, as areembodiments of semiconductor device structures including dual fins. Asused herein, the term “fin” includes a single, unitary, semiconductorstructure protruding from an active surface of a substrate. The methodsdisclosed herein may be used to fabricate a variety of devices such asdynamic random access memory (DRAM) devices, CMOS devices, and otherdevices in which fin-FETs would be suitable and increases in drivecurrent are desired.

Reference will now be made to the figures wherein like numeralsrepresent like elements. The figures are not necessarily drawn to scale.Elements in the figures are drawn in cross-section.

FIGS. 1-8A depict, in simplified cross-section or plan view, anembodiment of a process for forming dual fin structures on a substrate110. As used herein, the term “substrate” includes a base material orconstruction in and upon which various features may be formed. Variousembodiments of substrates include, but are not limited to, full orpartial wafers of semiconductor material (e.g., silicon, galliumarsenide, indium phosphide, etc.) and semiconductor-on-insulator (SOI)type substrates such as silicon-on-ceramic (SOC), silicon-on-glass(SOG), and silicon-on-sapphire (SOS) substrates. In some embodiments, asemiconductor device structure 100 includes a substrate 110 and a masklayer 120, as shown in FIG. 1.

In some embodiments, a mask layer 120 may be formed on the substrate 110by depositing a dielectric material, such as silicon nitride (Si₃N₄) orsilicon dioxide (SiO₂), by conventional techniques, including, but notlimited to, chemical vapor deposition (CVD), pulsed layer deposition(PLD), atomic layer deposition (ALD), and the like. In otherembodiments, material of mask layer 120 may be applied and spread across(e.g., by spin-on processes) the substrate 110, grown on the substrate110, or formed by other suitable techniques.

As shown in FIG. 2A, the mask layer 120 may be patterned by techniquesknown in the art to define a mask 120′. In some embodiments, the masklayer 120 may be patterned using known photomask forming and/ortransparent carbon mask forming and etching techniques. Removal of themask layer 120 may be used to form a mask 120′ with apertures 130through which regions 140 of the substrate 110 are exposed. The mask120′ may be defined to form multiple exposed regions 140 useful informing an array of fin-FET devices. FIG. 2B illustrates the mask 120′formed over substrate 110, with apertures 130 located over a pluralityof exposed regions 140 from which semiconductor device features are tobe defined.

Referring to FIG. 3, trenches 150 for shallow trench isolation (STI)structures may be formed by removing material from portions of thesubstrate 110. In some embodiments, the trenches 150 may be formed byetching the exposed regions 140 of the substrate 110 through apertures130 in the mask 120′. In some embodiments, the mask 120′ may comprise ahard mask of silicon nitride material, and the substrate 110 may be asilicon material that is selectively etched with respect to the mask120′. In some embodiments, an anisotropic etch (e.g., a dry plasma etch)may be used to remove substrate 110 material to form trenches 150 withsloped or angled sidewalls 160 such as those shown in FIG. 3. In otherembodiments, an isotropic etch (e.g., a wet etch) may be used to removesubstrate 110 material to form trenches 150, with or without sloped orangled sidewalls 160. In some embodiments, removal of material from thesubstrate 110 is controlled to form trenches 150 with depths of about140 Å to about 14,000 Å. In specific embodiments, material may beremoved from the substrate 110 to form trenches 150 with depths of about2,500 Å.

During the formation of trenches 150, spade-shaped recesses 165 (seeFIGS. 11 and 13), which may also be characterized as generallysemicircular in configuration, may optionally be formed in the trenchsidewalls 160. In some embodiments, a so-called “spade etch” process maybe employed as material is removed from the substrate 110 to form thetrench 150 to isotropically remove portions of the substrate 110 fromsidewalls 160. The recesses 165 may be formed after the trench 150 hasbeen defined, or as an intermediate part of the process for defining thetrench 150 (i.e., definition of the trench 150 may be discontinued toform the recesses 165 and, once the recesses 165 are formed, definitionof the trenches 150 may continue by resuming the initial process bywhich material was removed from the substrate 110, or by a similarmaterial removal process). The recess 165 may be used, as depicted inFIGS. 11 and 13 and described in detail below, to form isolation regions250 that may be useful in reducing cross-talk and leakage currentthrough the substrate 110.

Active device areas on an active surface 112 of substrate 110 may befurther isolated from one another by known shallow trench isolation(STI) techniques. As shown in FIG. 4, a dielectric material 170, such assilicon dioxide (SiO₂), may be applied over the active surface 112 ofthe substrate 110. Deposition of the dielectric material 170 may beperformed by techniques known in the art, such as chemical vapordeposition (CVD) and spin-on techniques. The dielectric material 170overlies mask 120′ and fills both trenches 150 in the substrate 110 andapertures 130 (FIG. 2A) in the mask 120′. In embodiments where a spadeetch is used to form spade-shaped recesses 165 (e.g., FIG. 11) in thesidewalls 160 of the trenches 150, the dielectric material 170 fills therecesses 165, resulting in isolation regions 250 such as those shown inFIGS. 11 and 13.

Referring to FIG. 5, a portion of the dielectric material 170 may beremoved from over the mask 120′ to expose the mask 120′ and to separatethe newly formed STI structures 200 from one another. In someembodiments, a chemical-mechanical polishing (CMP) process may be usedto remove the dielectric material 170 that overlies the mask 120′ sothat an upper surface of each resulting STI structure 200 issubstantially coplanar, or level, with the upper surface of the mask120′. In such embodiments, the mask 120′ may comprise a material that isremoved at a lower rate during polishing than the dielectric material170 and may, therefore, be used as a CMP-stop layer to prevent removalof material covered by the mask 120′. Where the STI structures 200include silicon dioxide, the mask 120′ may include silicon nitride. Inother embodiments, the dielectric material 170 may be selectivelyremoved (e.g., etched) to expose the mask 120′, which may serve as anetch stop. The resulting semiconductor device structure 100 includes anexposed mask 120′ in the form of a hard mask on protruding regions 155of the active surface 112 of the substrate 110 that are located betweena pair of STI structures 200.

Referring to FIG. 6, a portion of the mask 120′ and material of theprotruding region 155 may be removed to define a recess 180 with dualfin structures 190 a and 190 b on opposite sides of the recess 180. Aportion of the mask 120′ may be removed to expose the protruding region155 where the recess 180 will be formed. In some embodiments, materialof the mask 120′ may be selectively removed (e.g., etched) using the STIstructures 200 as a self-aligned hard mask.

After removal of portions of the mask 120′, a portion of each protrudingregion 155 may be removed through remaining portions of the mask 120′ todefine the recess 180 and the dual fin structures 190 a and 190 b. Insome embodiments, the STI structures 200 and the mask 120′ may be usedas self-aligning hard masks in removing the substrate 110 material fromeach protruding region 155. In one embodiment, silicon of the substrate110 may be selectively removed with respect to a silicon nitride of themask 120′ and silicon dioxide of the STI structures 200.

The shape and critical dimensions (CD) of the recess 180 and the dualfin structures 190 a and 190 b may be controlled by the process by whichmaterial is removed from each protruding region 155 of the substrate110. In some embodiments, removal of material from the substrate 110 isperformed using an anisotropic etch process, as known in the art, toform sloped or angled sidewalls 160, such those shown in FIG. 6. In someembodiments, the material of the substrate 110 may be removed to form aV-shaped recess 270, as shown in FIG. 14, or a U-shaped recess 280, asshown in FIG. 15. In some embodiments, the recess 180 extends into thesubstrate 110 to a depth of about 40 Å to about 4,000 Å. In a specificembodiment, the recess 180 may extend about 1,000 Å into the substrate110.

Cross-talk and leakage current through the substrate 110 may be reduced,in additional embodiments, by electrically isolating the dual finstructures 190 a and 190 b from each other. The dual fin structures 190a and 190 b may be at least partially isolated from the substrate 110and from each other by forming an enlarged end 260 (e.g., FIG. 12) atthe base of the recess 180 (or at the end of recess 270, 280, etc.), inthe substrate 110, between and at least partially beneath the dual finstructures 190 a and 190 b, such as the bowl-shaped recess 180 depictedin FIG. 12. Better isolation may be obtained the further the enlargedend 260 extends beneath each of the dual fin structures 190 a, 190 b.

In some embodiments, the enlarged end 260 may be formed using a “bowletch.” A bowl etch may be performed as described in United States PatentApplication Publication No. 2006/0292787 to Wang et al., referred toherein as “Wang,” which was published on Dec. 28, 2006, the disclosureof which is hereby incorporated herein by reference in its entirety. Aliner, such as silicon dioxide, is formed on surfaces of the recess 180(i.e., on the opposed surfaces of the dual fin structures 190 a and 190b) while an overlying mask layer remains unlined. An anisotropic etch isused to remove a portion of the liner at the base of the recess 180,leaving liner material on sidewalls 160 of the recess 180. Withremaining portions of the liner protecting the sidewalls 160 of therecess 180, an isotropic etch is performed to form a bowl-shaped regionin the unlined bottom of the recess 180. Such a method results in anenlarged end 260 at the base of the recess 180.

While, in the embodiment shown in FIG. 12, the dual fin structures 190 aand 190 b are partially electrically isolated from the substrate 110, inother embodiments, current leakage and cross-talk through the substrate110 may be further reduced or even eliminated by further electricallyisolating the dual fin structures 190 a and 190 b from the substrate110. In such embodiments, a combination of a spade etch, describedherein with respect to FIG. 11, and a bowl etch, described herein withrespect to FIG. 12, may be employed. The spade etch may be performedsubsequent to or during the formation of trenches 150 in the substrate110. As dielectric material 170 is introduced into the trenches 150(FIG. 4), the recesses 165 (FIG. 13) formed by the spade etch are alsofilled with dielectric material to form isolation regions 250 (FIG. 13).The bowl etch may be performed after formation of the recess 180, asdescribed above in reference to FIG. 12. Combining the etching processesresults in an embodiment of a semiconductor device structure 100 inwhich the dual fin structures 190 a and 190 b are further electricallyisolated from the substrate 110 and from one another, as illustrated inFIG. 13.

Referring now to FIG. 7, portions of the STI structures 200 are removedto expose the outer surfaces of the dual fin structures 190 a and 190 b.In some embodiments, the STI structures 200 are selectively etched backin relation to the mask 120′ and the substrate 110. In some embodiments,the STI structure 200 may be recessed a depth of about 20 Å to about20,000 Å and a width of from about 30 Å to about 50 Å at an uppersurface of the STI structure 200. In some embodiments, removal of aportion of the STI structure 200 results in an upper surface 205 of theSTI structure 200 that is substantially coplanar with a lower surface206 of the recess 180. In other embodiments, an elevation (in thedepicted orientation) of the upper surface 205 may be below an elevationof the lower surface 206 of the recess 180.

As shown in FIG. 8A, remaining portions of the mask 120′ may be removedfrom the upper surfaces of the dual fin structures 190 a and 190 b. Insome embodiments, material of the mask 120′ may be selectively etchedover the substrate 110 and the STI structures 200. In some embodiments,removal of the mask 120′ results in dual fin structures 190 a and 190 bwith substantially planar upper surfaces 191 a and 191 b, such as thosedepicted in FIG. 8A. FIG. 8B is a plan view of the semiconductor devicestructure 100, with dual fin structures 190 a and 190 b on oppositesides of a recess 180, as shown in FIG. 8A.

The dual fin structures 190 a and 190 b disclosed herein can be used toincrease drive current in a DRAM device, a CMOS device, or other memorydevices. In various embodiments of the present disclosure, these andother devices may be fabricated using known processes. In someembodiments, the dual fin structures 190 a and 190 b may be used to formthe channel regions of a semiconductor device, such as a fin-FET device.

FIG. 9 is a perspective view of the semiconductor device structure 100shown in FIG. 8A. The dual fin structures 190 a and 190 b form channelregions 210 extending between source/drain regions 220 with STIstructures 200 providing isolation between adjacent active deviceregions. In some embodiments, the source/drain regions 220 of thesemiconductor device structure 100 may be doped using any suitabledoping process, such as ion implantation or diffusion.

Referring to FIG. 10, a gate oxide film 230 may be formed between thesource/drain regions 220 on the semiconductor device structure 100 byknown oxidation processes (e.g., thermal oxidation, exposure to anoxidant, etc.), deposited (e.g., by CVD, PLD, ALD, etc.), or formed byother processes known in the art. A gate electrode 240 may be formed onthe gate oxide film 230 to form a transistor gate, such as that shown inFIG. 10. In some embodiments, a single-gate fin-FET may be formed byforming a continuous gate electrode 240 over the surfaces of the dualfin structures 190 a and 190 b and the recess 180. Other features of thefin-FET, such as dielectric and protective structures, may be formed byknown processes.

In some embodiments, the semiconductor device structure 100 with dualfin structures 190 a and 190 b may be used to form a dual-gate fin-FETby forming separate gate electrodes 240 over at least one side of eachof the dual fin structures 190 a and 190 b. In a specific embodiment, agate electrode may be formed on the outer surface of both dual finstructures 190 a and 190 b to form a double-gate fin-FET (not shown). Inother embodiments, a triple-gate fin-FET (not shown) may be fabricatedby forming a three-gate electrode.

Fin-FET devices described herein may be used in embodiments ofelectronic systems of the present disclosure. For example, FIG. 16 is ablock diagram of an illustrative electronic system 300 according to thepresent disclosure. The electronic system 300 may comprise, for example,a computer or computer hardware component, a server or other networkinghardware component, a cellular telephone, a digital camera, a personaldigital assistant (PDA), portable media (e.g., music) player, etc. Theelectronic system 300 includes at least one memory device 301. Theelectronic system 300 further may include at least one electronic signalprocessor device 302 (often referred to as a “microprocessor”). At leastone of the electronic signal processor device 302 and the at least onememory device 301 may comprise, for example, an embodiment of thesemiconductor device structure 100 shown in FIGS. 1-15. Stated anotherway, at least one of the electronic signal processor device 302 and theat least one memory device 301 may comprise an embodiment of atransistor having dual fins as previously described in relation to thesemiconductor device structure 100. The electronic system 300 mayfurther include one or more input devices 304 for inputting informationinto the electronic system 300 by a user, such as, for example, a mouseor other pointing device, a keyboard, a touchpad, a button, or a controlpanel. The electronic system 300 may further include one or more outputdevices 306 for outputting information (e.g., visual or audio output) toa user such as, for example, a monitor, a display, a printer, an audiooutput jack, a speaker, etc. In some embodiments, the input device 304and the output device 306 may comprise a single touchscreen device thatcan be used both to input information to the electronic system 300 andto output visual information to a user. The one or more input devices304 and output devices 306 may communicate electrically with at leastone of the memory device 301 and the electronic signal processor device302.

Although the foregoing description includes many specifics, these shouldnot be construed as limiting the scope of the present disclosure but,merely, as providing illustrations of some of the presently preferredembodiments. Similarly, other embodiments of the disclosure may bedevised which do not depart from the scope of the present disclosure.Features from different embodiments may be employed in combination. Thescope of the disclosure is, therefore, indicated and limited only by theappended claims and their legal equivalents, rather than by theforegoing description. All additions, deletions, and modifications tothe disclosure as disclosed herein which fall within the meaning andscope of the claims are to be embraced thereby.

What is claimed is:
 1. A method for fabricating a semiconductor device,the method comprising: forming at least two trenches in a substratethrough apertures defined in a mask material overlying the substrate;forming a dielectric material in the at least two trenches; defininganother aperture extending through the mask material and having an upperedge defined at least in part by trenches of the at least two trenchesto expose a region of the substrate, the region disposed between two ofthe at least two trenches; and forming a recess in the region of thesubstrate.
 2. The method of claim 1, wherein: forming a recess in theregion of the substrate comprises utilizing portions of the dielectricmaterial as another mask to selectively etch the mask material and theregion of the substrate.
 3. The method of claim 2, further comprisingremoving portions of the dielectric material in the at least twotrenches to recess the dielectric material in the at least two trenchesrelative to a lower recess surface of the recess in the region of thesubstrate.
 4. The method of claim I., wherein forming the at least twotrenches comprises forming at least two trenches each defining a trenchsidewall and a trench sidewall recess in the trench sidewall.
 5. Themethod of claim 4, wherein forming a dielectric material in the at leasttwo trenches comprises filling the at least two trenches and the trenchsidewall recess of each of the at least two trenches with the dielectricmaterial.
 6. The method of claim 5, wherein forming a recess in theregion of the substrate comprises exposing the dielectric materialwithin the trench sidewall recess.
 7. A method for fabricating asemiconductor device, the method comprising: forming a mask materialover at least a region of a substrate; and forming a recess extendingthrough the mask material and in the region of the substrate laterallyadjacent to regions of dielectric material to define structuresseparating the recess from the regions of dielectric material, therecess having an entrance extending between one region of the regions ofdielectric material to another region of the regions of dielectricmaterial, the entrance defined at least in part by the mask material. 8.The method of claim 7, further comprising forming the regions ofdielectric material in the substrate, an upper surface of the regions ofdielectric material being coplanar with an upper surface of the maskmaterial.
 9. The method of claim 7, further comprising removing the maskmaterial to expose horizontal surfaces of the structures.
 10. The methodof claim 7, further comprising removing a portion of the dielectricmaterial to lower an upper surface of the dielectric material relativeto the structures.
 11. The method of claim 7, further comprising, afterforming the recess, removing a portion of the substrate to enlarge anend of the recess to define an enlarged end protruding at leastpartially beneath the structures.
 12. The method of claim 7, whereinforming a recess comprises forming a V-shaped recess in the region ofthe substrate.
 13. The method of claim 7, wherein forming a recesscomprises forming a U-shaped recess in the region of the substrate. 14.A method for fabricating a semiconductor device, the method comprising:forming trenches in a substrate through a mask material; forming adielectric material over the mask material and in the trenches to fillthe trenches with the dielectric material; exposing a portion of themask material through the dielectric material; and forming a recess inthe substrate through the portion of the mask material, leaving at leasta remnant portion of the mask material adjacent the recess, the recessdefined at least in part by the dielectric material.
 15. The method ofclaim 14, wherein exposing a portion of the mask material through thedielectric material comprises removing a portion of the dielectricmaterial elevated above the mask material.
 16. The method of claim 14,further comprising removing the mask material to expose structuresdefined in the substrate between the recess and the trenches.
 17. Themethod of claim 14, wherein forming a recess comprises forming therecess between sidewalls of the substrate and through the portion of themask material.
 18. The method of claim 14, wherein forming a recesscomprises forming the recess centrally between the trenches.
 19. Themethod of claim 14, further comprising, after forming the trenches,laterally extending the trenches beneath portions of the substrate.